CY8C201A0-LDX2I Operating Modes of I2C Commands

CY8C201A0-LDX2I Operating Modes of I2C Commands
Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The timings remain approximately the same for
different configurations of the slave. To reduce the
acknowledgment times in normal mode, the registers
0x06–0x09, 0x0C, 0x0D, 0x10–0x17, 0x50, 0x51, 0x57–0x60,
0x7E are given only read access. Write to these registers can be
done only in setup mode.
Setup Mode
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.

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Features
■ Capacitive slider and button input
? Choice of configurations:
? 10-segment slider
? 5-segment slider with remaining 5 pins configurable as
CapSense
?
 or GPIO
? Robust sensing algorithm
? High sensitivity, low noise
? Immunity to RF and AC noise.
? Low radiated EMC noise
? Supports wide range of input capacitance, sensor shapes,
and sizes
■ Target applications
? Printers
? Cellular handsets
? LCD monitors
? Portable DVD players
■ Low operating current
? Active current: continuous sensor scan: 1.5 mA
? Deep sleep current: 4 μA
■ Industry's best configurability
? Custom sensor tuning, one optional capacitor
? Output supports strong drive for LED
? Output state can be controlled through I
2
C or directly from
CapSense input state
? Run time reconfigurable over I
2
C
■ Advanced features
? Interrupt outputs
? User defined Inputs
? Wake on interrupt input
? Sleep control pin
? Nonvolatile storage of custom settings
? Easy integration into existing products – configure output to
match system
? No external components required
? World class free configuration tool
■ Wide range of operating voltages
? 2.4 V to 2.9 V
? 3.10 V to 3.6 V
? 4.75 V to 5.25 V
■ I
2
C communication
? Supported from 1.8 V
? Internal pull-up resistor support option
? Data rate up to 400 kbps
? Configurable I
2
C addressing
■ Industrial temperature range: –40 °C to +85 °C.
■ Available in 16-pin QFN and 16-pin SOIC Package

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 Low power CapSense
®
 block
 Configurable capacitive sensing elements
 Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
 Powerful Harvard-architecture processor
 M8C processor speeds running up to 12 MHz
 Low power at high speed
 Operating voltage: 2.4 V to 5.25 V
 Industrial temperature range: –40 °C to +85 °C
 Flexible on-chip memory
 8 KB flash program storage 50,000 erase/write cycles
 512-Bytes SRAM data storage
 Partial flash updates
 Flexible protection modes
 Interrupt controller
 In-system serial programming (ISSP)
 Complete development tools
 Free development tool (PSoC Designer™)
 Full-featured, in-circuit emulator, and programmer
 Full-speed emulation
 Complex breakpoint structure
 128 KB trace memory
 Precision, programmable clocking
 Internal ±5.0% 6- / 12-MHz main oscillator
 Internal low speed oscillator at 32 kHz for watchdog and sleep
 Programmable pin configurations
 Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
 Up to 28 analog inputs on all GPIOs
 Configurable inputs on all GPIOs
 20-mA sink current on all GPIOs
 Selectable, regulated digital I/O on port 1
 3.0 V, 20 mA total port 1 source current
 5 mA strong drive mode on port 1 versatile analog mux
 Common internal analog bus
 Simultaneous connection of I/O combinations
 Comparator noise immunity
 Low-dropout voltage regulator for the analog array
 Additional system resources
 Configurable communication speeds
 I2C: selectable to 50 kHz, 100 kHz, or 400 kHz
 SPI: configurable between 46.9 kHz and 3 MHz
 I2C slave
 SPI master and SPI slave
 Watchdog and sleep timers
 Internal voltage reference
 Integrated supervisory circuit

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 Low power CapSense® block
 Configurable capacitive sensing elements
 Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
 Powerful Harvard-architecture processor
 M8C processor speeds running up to 12 MHz
 Low power at high speed
 Operating voltage: 2.4 V to 5.25 V
 Industrial temperature range: –40 °C to +85 °C
 Flexible on-chip memory
 8 KB flash program storage 50,000 erase/write cycles
 512-Bytes SRAM data storage
 Partial flash updates
 Flexible protection modes
 Interrupt controller
 In-system serial programming (ISSP)
 Complete development tools
 Free development tool (PSoC Designer™)
 Full-featured, in-circuit emulator, and programmer
 Full-speed emulation
 Complex breakpoint structure
 128 KB trace memory
 Precision, programmable clocking
 Internal ±5.0% 6- / 12-MHz main oscillator
 Internal low speed oscillator at 32 kHz for watchdog and sleep
 Programmable pin configurations
 Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
 Up to 28 analog inputs on all GPIOs
 Configurable inputs on all GPIOs
 20-mA sink current on all GPIOs
 Selectable, regulated digital I/O on port 1
 3.0 V, 20 mA total port 1 source current
 5 mA strong drive mode on port 1 versatile analog mux
 Common internal analog bus
 Simultaneous connection of I/O combinations
 Comparator noise immunity
 Low-dropout voltage regulator for the analog array
 Additional system resources
 Configurable communication speeds
 I2C: selectable to 50 kHz, 100 kHz, or 400 kHz
 SPI: configurable between 46.9 kHz and 3 MHz
 I2C slave
 SPI master and SPI slave
 Watchdog and sleep timers
 Internal voltage reference
 Integrated supervisory circuit

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 Low power CapSense® block
 Configurable capacitive sensing elements
 Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
 Powerful Harvard-architecture processor
 M8C processor speeds running up to 12 MHz
 Low power at high speed
 Operating voltage: 2.4 V to 5.25 V
 Industrial temperature range: –40 °C to +85 °C
 Flexible on-chip memory
 8 KB flash program storage 50,000 erase/write cycles
 512-Bytes SRAM data storage
 Partial flash updates
 Flexible protection modes
 Interrupt controller
 In-system serial programming (ISSP)
 Complete development tools
 Free development tool (PSoC Designer™)
 Full-featured, in-circuit emulator, and programmer
 Full-speed emulation
 Complex breakpoint structure
 128 KB trace memory
 Precision, programmable clocking
 Internal ±5.0% 6- / 12-MHz main oscillator
 Internal low speed oscillator at 32 kHz for watchdog and sleep
 Programmable pin configurations
 Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
 Up to 28 analog inputs on all GPIOs
 Configurable inputs on all GPIOs
 20-mA sink current on all GPIOs
 Selectable, regulated digital I/O on port 1
 3.0 V, 20 mA total port 1 source current
 5 mA strong drive mode on port 1 versatile analog mux
 Common internal analog bus
 Simultaneous connection of I/O combinations
 Comparator noise immunity
 Low-dropout voltage regulator for the analog array
 Additional system resources
 Configurable communication speeds
 I2C: selectable to 50 kHz, 100 kHz, or 400 kHz
 SPI: configurable between 46.9 kHz and 3 MHz
 I2C slave
 SPI master and SPI slave
 Watchdog and sleep timers
 Internal voltage reference
 Integrated supervisory circuit

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The PSoC family consists of many Programmable
System-on-Chips with On-Chip Controller devices. These
devices are designed to replace multiple traditional MCU based
system components with one low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks and programmable interconnect. This architecture
enables the user to create customized peripheral configurations
to match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The PSoC architecture for this device family, as shown in
Figure 1, consists of three main areas: the Core, the System
Resources, and the CapSense Analog System. A common
versatile bus enables connection between I/O and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose I/O (GPIO) are also
included. The GPIO provide access to the MCU and analog mux.

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The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO, and ILO.
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a two MIPS, 8-bit
Harvard-architecture microprocessor.
System Resources provide additional capability such as a
configurable I
2
C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
The Analog System consists of the CapSense PSoC block and
an internal 1.8 V analog reference. Together they support

capacitive sensing of up to 28 inputs.

CY8C20111-SX1I PSoC Functional Overview

CY8C20111-SX1I PSoC Functional Overview
The PSoC family consists of many Programmable
System-on-Chips with On-Chip Controller devices. These
devices are designed to replace multiple traditional MCU based
system components with one low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks and programmable interconnect. This architecture
enables the user to create customized peripheral configurations
to match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The PSoC architecture for this device family, as shown in
Figure 1, consists of three main areas: the Core, the System
Resources, and the CapSense Analog System. A common
versatile bus enables connection between I/O and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose I/O (GPIO) are also
included. The GPIO provide access to the MCU and analog mux.

CY8C20111-SX1I PSoC Core

CY8C20111-SX1I PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO, and ILO.
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a two MIPS, 8-bit
Harvard-architecture microprocessor.
System Resources provide additional capability such as a
configurable I
2
C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
The Analog System consists of the CapSense PSoC block and
an internal 1.8 V analog reference. Together they support

capacitive sensing of up to 28 inputs.

CY8C20111-SX1I CapSense Analog System

CY8C20111-SX1I CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins is
completed quickly and easily across multiple ports.
Figure 1.  Analog System Block Diagram
Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
 Complex capacitive sensing interfaces such as sliders and
touch pads
 Chip-wide mux that enables analog input from any I/O pin
 Crosspoint connection between any I/O pin combinations

CY8C20111-SX1I Additional System Resources

CY8C20111-SX1I Additional System Resources
System Resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. Brief statements describing the
merits of each system resource follow:
 The I2C slave or SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
 Low voltage detection (LVD) interrupts signal the application

of
falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
 An internal 1.8 V reference provides an absolute reference for
capacitive sensing.
 The 5 V maximum input, 3 V fixed output, low dropout regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.

CY8C20111-SX1I Development Tools

CY8C20111-SX1I Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and

digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■ Application editor graphical user interface (GUI) for device

and
user module configuration and dynamic reconfiguration
■ Extensive user module catalog
■ Integrated source-code editor (C and assembly)
■ Free C compiler with no size restrictions or time limits
■ Built-in debugger
■ In-circuit emulation
■ Built-in support for communication interfaces:
❐ Hardware and software I
2
C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous

receiver/transmitters (UARTs), SPI master and slave, and

wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.

CY8C20111-SX1I Additional System Resources

CY8C20111-SX1I Additional System Resources
System Resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. Brief statements describing the
merits of each system resource follow:
 The I2C slave or SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
 Low voltage detection (LVD) interrupts signal the application

of
falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
 An internal 1.8 V reference provides an absolute reference for
capacitive sensing.
 The 5 V maximum input, 3 V fixed output, low dropout regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.

CY8C20111-SX1I CapSense Analog System

CY8C20111-SX1I CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins is
completed quickly and easily across multiple ports.
Figure 1.  Analog System Block Diagram
Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
 Complex capacitive sensing interfaces such as sliders and
touch pads
 Chip-wide mux that enables analog input from any I/O pin
 Crosspoint connection between any I/O pin combinations

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Features
 True dual-ported memory cells which enable simultaneous
access of the same memory location
 4, 8 or 16 K × 16 organization
(CY7C024AV/025AV/026AV)
 0.35 micron CMOS for optimum speed and power
 High speed access: 20 ns and 25 ns
 Low operating power
 Active: ICC = 115 mA (typical)
 Standby: ISB3
= 10 ?A (typical)
 Fully asynchronous operation
 Automatic power down
 Expandable data bus to 32 bits or more using Master and Slave
chip select when using more than one device
 On chip arbitration logic
 Semaphores included to permit software handshaking
between ports
 INT flag for port-to-port communication
 Separate upper byte and lower byte control
 Pin select for Master or Slave (M/S)
 Commercial and industrial temperature ranges
 Available in 100-pin Pb-free TQFP and 100-pin TQFP

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The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are
low-power CMOS 4K × 16/18 and 8K × 16/18 dual-port static
RAMs. Various arbitration schemes are included on the
CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The CY7C024E/CY7C0241E and
CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32-/36-bit or wider master/ slave dual-port static
RAM. An M/S pin is provided for implementing 32-/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the  same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a CE pin.
The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are
available in 100-pin Pb-free TQFP.

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Features
 True dual-ported memory cells that allow simultaneous reads
of the same memory location
 4K ×16 organization (CY7C024E)
 4K × 18 organization (CY7C0241E)
 8K × 16 organization (CY7C025E)
 8K × 18 organization (CY7C0251E)
 0.35-μ complementary metal oxide semiconductor (CMOS) for
optimum speed and power
 High-speed access: 15 ns
 Low operating power: ICC = 180 mA (typ), ISB3
 = 0.05 mA (typ)
 Fully asynchronous operation
 Automatic power-down
 Expandable data bus to 32/36 bits or more using master/slave
chip select when using more than one device
 On-chip arbitration logic
 Semaphores included to permit software handshaking
between ports
 INT flag for port-to-port communication
 Separate upper-byte and lower-byte control
 Pin select for master or slave
 Available in Pb-free 100-pin thin quad flatpack (TQFP) package

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 True dual-ported memory cells which enable simultaneous
access of the same memory location
 4, 8 or 16 K × 16 organization
(CY7C024AV/025AV/026AV)
 0.35 micron CMOS for optimum speed and power
 High speed access: 20 ns and 25 ns
 Low operating power
 Active: ICC = 115 mA (typical)
 Standby: ISB3
= 10 ?A (typical)
 Fully asynchronous operation
 Automatic power down
 Expandable data bus to 32 bits or more using Master and Slave
chip select when using more than one device
 On chip arbitration logic
 Semaphores included to permit software handshaking
between ports
 INT flag for port-to-port communication
 Separate upper byte and lower byte control
 Pin select for Master or Slave (M/S)
 Commercial and industrial temperature ranges
 Available in 100-pin Pb-free TQFP and 100-pin TQFP

CY7C024AV-20AXI chip decryption

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True dual-ported memory cells which enable simultaneous
access of the same memory location
 4, 8 or 16 K × 16 organization
(CY7C024AV/025AV/026AV)
0.35 micron CMOS for optimum speed and power
 High speed access: 20 ns and 25 ns
 Low operating power
 Active: ICC = 115 mA (typical)
 Standby: ISB3
= 10 ?A (typical)
 Fully asynchronous operation

Automatic power down
 Expandable data bus to 32 bits or more using Master and Slave
chip select when using more than one device
 On chip arbitration logic
 Semaphores included to permit software handshaking
between ports
 INT flag for port-to-port communication
 Separate upper byte and lower byte control
 Pin select for Master or Slave (M/S)
 Commercial and industrial temperature ranges
 Available in 100-pin Pb-free TQFP and 100-pin TQFP

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The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are
low-power CMOS 4K × 16/18 and 8K × 16/18 dual-port static
RAMs. Various arbitration schemes are included on the
CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The CY7C024E/CY7C0241E and
CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32-/36-bit or wider master/ slave dual-port static
RAM. An M/S pin is provided for implementing 32-/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the  same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a CE pin.
The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are
available in 100-pin Pb-free TQFP.

The M32C/8B Key Features

Key Features:

16-bit Multifunction Timer (Timer A and B, incl. 3-phase

inverter motor control function): 11 channels
Clock Synchronous / Asynchronous Serial Interface: 5 channels
10-bit A/D Converter: 34 channels* (in single-chip mode)
18 channels* (in memory expansion mode and microprocessor mode)
8-bit D/A Converter: 2
DMAC: 4 channels
DMAC II: Can be activated by all peripheral function interrupt

factors
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Clock Generation Circuits: Main Clock Generation Circuit, Sub

Clock Generation Circuit, On-chip Oscillator, PLL Synthesizer
Oscillation Stop Detection Function
Power Supply Voltage Detection
I/O Ports: 121* (in single-chip mode)
81* (in memory expansion and microprocessor mode with 8-bit

external bus)
73* (in memory expansion and microprocessor mode with 16-bit

external bus)
External Interrupt Pins: 11 (in single-chip mode)
11 (in memory expansion and microprocessor mode with 8-bit

external bus)
8 (in memory expansion and microprocessor mode with 16-bit

external bus)
Data Flash: 4KB × 2 blocks (Flash Memory Version only)
*: Spec of 144-pin version.

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The M32C/8B is based on the M32C/80 CPU Core and has 16MB of

address space. Maximum operating frequency is 32MHz. Flash

Memory and ROM-less Versions are available. Internal Flash

Memory is programmable on a single power source.

M16C PLATFORM

M16C PLATFORM: The M16C Family offers a robust platform of

32/16-bit CISC microcomputers featuring high ROM code

efficiency, extensive EMI/EMS noise immunity, ultra-low power

consumption, high-speed processing in actual applications, and

numerous and varied integrated peripherals. Extensive device

scalability from low- to high-end, featuring a single

architecture as well as compatible pin assignments and

peripheral functions, provides support for a vast range of

application fields. In addition, our low-cost development

environment and program correction function help you shorten

product development time while greatly reducing total system

costs.

R8C/Tiny Series Key Applications

From the R8C/Tiny Series to the R8C Family

Key Applications

Audio Equipment, TV, Cameras
Communication/Portable Equipment
Electronic Household Appliances (incl. Inverter Solution), Motor

Control, Housing Equipment (Sensors, Security Systems)
Office Equipment, General Industrial Equipment, Consumer

Products
Automotive (incl. Body, Safety, Audio)

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M16C PLATFORM: The M16C Family offers a robust platform of

32/16-bit CISC microcomputers featuring high ROM code

efficiency, extensive EMI/EMS noise immunity, ultra-low power

consumption, high-speed processing in actual applications, and

numerous and varied integrated peripherals. Extensive device

scalability from low- to high-end, featuring a single

architecture as well as compatible pin assignments and

peripheral functions, provides support for a vast range of

application fields. In addition, our low-cost development

environment and program correction function help you shorten

product development time while greatly reducing total system

costs.

From the R8C/Tiny Series to the R8C Family

Key Applications

Audio Equipment, TV, Cameras
Communication/Portable Equipment
Electronic Household Appliances (incl. Inverter Solution), Motor

Control, Housing Equipment (Sensors, Security Systems)
Office Equipment, General Industrial Equipment, Consumer

Products
Automotive (incl. Body, Safety, Audio)